Exemplary embodiments of the present invention relate to a semiconductor device fabricating method, and more particularly, to a semiconductor device with buried bit lines and a method for fabricating the same.
For high integration of a memory device such as a DRAM, memory cells having a 4F2 (where F is a minimum feature size) structure are desirable, where such cells may increase a net die compared to cells having 8F2 and 6F2 structures.
A cell having the 4F2 structure may be a three-dimensional cell which includes a vertical transistor and a buried bit line (BBL).
FIGS. 1A and 1B are a plan view and a cross-sectional view illustrating a conventional semiconductor device. FIG. 1A is a cross-sectional view of the conventional semiconductor device along the line A-A′ in FIG. 1B.
Referring to FIGS. 1A and 1B, a plurality of pillar-shaped active regions 12 are formed on a substrate 11. The active regions 12 are uniformly spaced from one another by trenches 13. A pad layer 14 and a hard mask layer 15 are deposited on the active regions 12. Buried bit lines BBL1, BBL2, BBL3 and BBL4 are formed in the trenches 13. Each of junctions 16 to serve as source regions or drain regions is formed on a portion of a sidewall of each of the active regions 12. The buried bit lines BBL1, BBL2, BBL3 and BBL4 and the junctions 16 are electrically connected through side contacts 17. Each of the side contacts 17 may be formed on the portion of just one sidewall of each of the active regions 12. This is called an OSC (one side contact) structure. The reference numerals 18 and 19 designate dielectric layers such as liner layers or any other reasonably suitable dielectric layers.
In the semiconductor device shown in FIGS. 1A and 1B, due to the fact that the side contacts 17 are used at zones where the buried bit lines BBL1, BBL2, BBL3 and BBL4 and the active regions 12 contact each other, ohmic contacts may be formed. The side contacts 17 and the junctions 16 are formed on a portion of a sidewall of each of the active regions 12. The junctions 16 are also called side junctions.
However, in the conventional art, in using an etching process for exposing a sidewall of each of the active regions 12 to form the junctions 16 and the side contacts 17, it is difficult to align appropriate mask(s). Further, since the sidewall of each of the active regions 12 is exposed through the etching process, it is difficult to uniformly expose the portion of the sidewall. Accordingly, processing difficulties increase, and it is difficult to secure uniform characteristics of the side contacts 17 and the junctions 16. As a result, the electrical characteristics of the semiconductor device may be degraded.